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Chapter 1: Introduction
R
DDR2 Signaling
All DDR2 control signals are terminated through 47-? resistors to a 0.9-V VTT reference
voltage. The DDR2 interface of the FPGA supports SSTL18 signaling and all the DDR2
signals are controlled impedances. The DDR2 data, mask, and strobe signals are of
matched length within byte groups. On die termination (ODT) is available and better
performance can be achieved when used by the memory controller.
MIG Compatibility
MIG can be used to generate a compatible design for the Spartan-3A DSP 3400A Edition
board.
I 2 C Bus Addressing
The Spartan-3A DSP 3400A Edition board uses an I 2 C bus to interface different devices to
the FPGA. Because of the large amount of devices having similar slave address, an I 2 C
MUX (Philips PCA9544APW) is used to separate those devices from one to the other.
Table 1-29 defines the various slave addresses accessible by the FPGA through the I 2 C
MUX output.
Note : To change the I 2 C MUX output you need to perform a write access to the I 2 C MUX
(slave address 0xE4) with the following data: 0x04 for MUX 0, 0x05 for MUX 1, 0x06 for
MUX 2 and 0x07 for MUX3. See the I 2 C MUX data sheet for detailed information.
Table 1-29:
I 2 C Slave Device Addresses
I 2 C MUX
MUX 0
Device
Fan controller
I 2 C EEPROM
I 2 C MUX
Slave
Address
0x58
0xA8
0xE4
A7
0
1
1
A6
1
0
1
A5
0
1
1
A4
1
0
0
A3
1
1
0
A2
0
0
1
A1
0
0
0
A0
R/W
R/W
R/W
DDR2 SODIM EEPROM 0xA0
1
0
1
0
0
0
0
R/W
MUX 1
MUX 2
Clock generator
I 2 C MUX
FMC #1 I 2 C EEPROM
FMC #1 optional
FMC #2 I 2 C EEPROM
FMC #2 optional
Digital pot (adj. power
supply)
I 2 C MUX
0xD4
0xE4
0xA0
0xX0/0xX8
0xA2
0xX2/0xXA
0xA4
0xE4
1
1
1
X
1
X
1
1
1
1
0
X
0
X
0
1
0
1
1
X
1
X
1
1
1
0
0
X
0
X
0
0
0
0
0
X
0
X
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
42
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Spartan-3A DSP 3400A Edition User Guide
UG498 (v2.2) November 17, 2008
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